In semiconductor memory devices, data is read from or written to memory cells in the device according to decoded address information and various other control signals. Such memory devices are used for storage of data and/or program code in personal computer systems, embedded processor-based systems, video image processing circuits, communications devices, and the like. Ferroelectric memories store data in ferroelectric capacitors, and are commonly organized in single-transistor, single-capacitor (1T1C) or two-transistor, two-capacitor (2T2C) configurations. In a folded bitline 1T1C architecture, the individual ferroelectric memory cells typically include a ferroelectric (FE) capacitor adapted to store a binary data bit, together with a MOS access transistor, which operates to selectively connect the FE capacitor to one of a pair of complementary bitlines, with the other bitline being connected to a reference voltage for read operations. The individual cells are commonly organized as individual bits of a corresponding data word, where the cells of a given word are accessed concurrently by activation of platelines and wordlines by address decoding control circuitry.
Ferroelectric memory devices provide non-volatile data storage where the cell capacitors are constructed using ferroelectric dielectric material that may be polarized in one direction or another in order to store a binary data value. The ferroelectric effect in the cell capacitors provides retention of a stable polarization in the absence of an applied electric field due to the alignment of internal dipoles within perovskite crystals in the ferroelectric material. This alignment may be selectively achieved by application of an electric field in a first direction that exceeds a coercive field of the material. Conversely, reversal of the applied field reverses the internal dipoles, wherein the response of the polarization of a ferroelectric capacitor to the applied voltage may be plotted as a hysteresis curve.
Data in a typical ferroelectric memory device is read by connecting a reference voltage to a first bitline, and connecting the target cell capacitor between a complementary bitline and a plateline pulse signal. This provides a differential voltage on the bitline pair, which is connected to a differential sense amp circuit. The reference voltage is typically supplied at an intermediate voltage between the voltage associated with a capacitor storing a binary “0” and that of the capacitor storing a binary “1”. The polarity of the sensed differential voltage thus represents the data stored in the cell, which is buffered by the sense amp and provided to a pair of local IO lines. The transfer of data between the ferroelectric memory cell, the sense amp circuit, and the local data bitlines is controlled by various access transistors, typically MOS devices, with switching signals being provided by control circuitry including address decoders and timing circuits in the device.
Connection of the ferroelectric cell capacitor between an activated plateline and the bitline during a read operation causes an electric field to be applied to the cell capacitor. If the field is applied in a direction to switch or reverse the internal dipoles, more charge will be moved than if the dipoles are not reversed. As a result of this ferroelectric behavior, the sense amplifier can measure the charge applied to the cell bitlines and produce either a logic “1” or “0” differential voltage at the sense amp terminals. Since reading the cell data is a destructive operation, the sensed data is then restored to the cell following each read operation by application of another pulse to the cell platelines while the sense amp retains the latched data on the bitlines. To write data to the cell, an electric field is applied to the cell capacitor by a sense amp or write buffer in combination with a plateline activation pulse to polarize the capacitor to the desired data state.
Ferroelectric memory devices typically include a number of individually addressable memory cells arranged in an array configuration, wherein the array is typically organized as a matrix of rows and columns. Conventionally, data is stored into a memory array as a row, and read out from the memory array as a row, where the row typically consists of 8, 16, 32, or 64 bits of binary data. During a write operation, row decoder control circuitry provides a plateline pulse signal to the first sides of the ferroelectric cells in a data row, the other sides of which are connected to the array bitlines to receive the data. In a read operation, the decoder provides plateline pulses to the first side of each ferroelectric memory cell in a data row, and sense amplifiers are connected to the other side of the cells to sense a row of stored data bits in parallel fashion. Thus, in a single read operation, an entire row of data bits (e.g., 8, 16, 32, or 64 bits) are obtained from the memory cells in the selected row.
During a read operation in a typical folded-bitline array, a signal level V1 or V0 is obtained on the array data bitline, depending upon the state of the data being read from the cell (e.g., binary “1” or “0”, respectively). A reference voltage from a shared reference generator is ideally between V1 and V0, which is applied to the complementary bitline (e.g., a ‘reference’ bitline connected to the other input of the sense amp). To read the data, the cell transistor is turned on by applying a wordline activation voltage to the transistor gate to couple the cell capacitor to the data bitline. The plateline is then pulsed high, to cause charge sharing between the ferroelectric cell capacitor and the capacitance of the data bitline, by which the data bitline voltage rises, depending upon the state of the cell data being read. The plateline is then returned to 0V and the sense amp is activated, either during the plateline pulse (“step-sensing” or “on-pulse sensing”) or after the plateline signal is brought low (e.g., “pulse sensing” or “after-pulse sensing”). Following a cell data read, the data is restored to the cell by again pulsing the plateline high and then low while the wordline is asserted to reprogram the ferroelectric cell capacitor.
A continuing trend in the semiconductor device manufacturing industry is known as scaling, wherein components and interconnections in integrated circuits are scaled to ever higher density using smaller feature sizes. Another related trend is the reduction in voltage levels used in integrated circuits. For instance, whereas 3.3 V is typically found in devices fabricated using 0.25 um technology, only 1.5 V is typically found in 0.13 um devices. In conventional ferroelectric memory devices, the plateline pulse is generated from the supply voltage VCC. However, because the voltage across the cell capacitor during the plateline pulse is the difference between the plateline voltage and the data bitline voltage, the plateline pulse signal itself needs to be much higher than the coercive or saturation voltage of the capacitor. Reducing the device supply voltage thus makes it more difficult to ensure proper ferroelectric memory operation, since the thickness of the ferroelectric cell capacitors must continually be decreased in order for the ferroelectric capacitor to switch and therefore be useful as a memory element. Reducing the ferroelectric thickness increases the ratio of non-switched to switched charge in the material.
Several trends are also decreasing the amount of voltage that is available for use across the capacitor. These include decreased supply voltage VCC that is scaling (although not as fast when VCC approaches 1 V) and the need for constant bit line voltage for sensing that is not scaling, wherein the voltage across the capacitor during read operations is VCC−VBL, which is scaling faster than VCC. In addition, as ferroelectric device thickness is decreased in order to scale switching voltage, non-switched charge is increasing with scaling, while the switched charge is at best staying constant. As a result, the bitline voltage during read operations (VBL) is increasing for the same switched charge because the non-switched charge is increasing, whereby the useful voltage across the cell capacitor is effectively further reduced.
One possible approach involves designing voltage boost circuits to generate plateline pulse signals that are above the scaled supply voltage VCC. However, providing special high voltages for plateline pulse drivers increases the device area and cost, and can degrade device reliability. Thus, there is a need for improved ferroelectric memory devices and memory read techniques by which plateline voltage levels can be scaled or reduced for a given ferroelectric capacitor material type, without the need for voltage boost circuits.